library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( fx2_data : inout std_logic_vector(7 downto 0);
           fx2_read : out std_logic;
           fx2_write : out std_logic;
           serial_clk : in std_logic;
           serial_in : in std_logic;
           serial_out : in std_logic;
           serial_cs : in std_logic;
           serial_to_gc : out std_logic;
           debug_out : out std_logic);
end main;

architecture Behavioral of main is

signal byte: std_logic_vector(7 downto 0);
signal cnt: std_logic;
--signal tx: std_logic_vector(7 downto 0);

signal had_cs: std_logic;
signal cmd: std_logic_vector(11 downto 0);
signal cmd_counter: std_logic_vector(5 downto 0);
signal bit_counter: std_logic_vector(2 downto 0);
signal last_out: std_logic;

signal serial_my, serial_my_enable: std_logic;

signal prepare_hack: std_logic;
signal enable_hack: std_logic;

-- signal tc: std_logic_vector(8 downto 0);

signal insert_string: std_logic_vector(0 to (32*16)-1) := 
(
x"52000000" & x"3f60cc00" & x"3b800880" & x"7fa802a6" & x"60000000" & -- & x"3bbd0004" & 
-- x"3860ffff" & x"907b643c" & 
-- x"901b643c" &  
-- x"60000000" &
x"3bc00080" & x"3be00007" & x"48000011" & x"3fa08120" &
x"3be00003" & x"7fa803a6" & x"bf9b6814" & x"80bb6820" &
x"54a007ff" & x"4082fff8" &
-- x"7c00ebac" & 
--x"7c00efac" & 
--x"4c00012c" & 
 x"4e800020" 
-- x"60000000"
) xor

(
 -- because of copyright reasons, the XOR bytes are missing here.
 -- sorry.
 );

begin
	fx2_read <= '0';

--	debug_out <= serial_in;
	-- debug_out <=  '0';
	
	serial_to_gc <= ((serial_my and serial_my_enable) or (serial_in and not serial_my_enable))
			 when (serial_cs = '0') else 'Z';
	
--	serial_to_gc <= serial_in when (serial_cs = '0') else 'Z';
	
	--fx2_data <= tx;
	process (serial_cs, serial_clk)
	begin
		if (serial_cs = '1') then
			cnt <= '0';
			fx2_write <= '1';
			had_cs <= '1';
			cmd_counter <= (others => '0');
			bit_counter <= (0 => '1', others => '0');
			cmd <= (others => '0');
			serial_my_enable <= '0';
--			prepare_hack <= '0';
		else
			if (serial_clk'event and serial_clk='1') then

			if (conv_integer(cmd_counter) < 32) then
				cmd_counter <= cmd_counter + '1';
			end if;

			if ((enable_hack = '1') and (conv_integer(cmd(11 downto 0)) > 31) and (conv_integer(cmd(11 downto 0)) < 96)) then
				serial_my_enable <= '1';
			else
				serial_my_enable <= '0';
			end if;

			serial_my <= insert_string((conv_integer((cmd - 32)  & bit_counter)));

				if (bit_counter = 7) then
					if (cmd_counter = 32) then
						cmd <= cmd + '1';
					end if;
				end if;
				bit_counter <= bit_counter + '1';

				--tx <= serial_out & "0000000";

				if (had_cs = '1') then 
					enable_hack <= prepare_hack;
				end if;

				if (conv_integer(cmd) = 8) then
					prepare_hack <= '1';
				else
					prepare_hack <= '0';
				end if;

				if (cnt = '0') then
					fx2_data <= byte;
					fx2_write <= '0';
				else
					fx2_write <= '1';
				end if;
				-- serial_in statt last_out
				 byte(7 downto 0) <= byte(3 downto 0) & '0' & serial_out & (serial_my and serial_my_enable) & had_cs;
--				if (had_cs = '1') then
--					tc <= tc + '1';
--				end if;
				had_cs <= '0';
				cnt <= not cnt;
			end if;
		end if;
	end process;
end Behavioral;